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[VHDL-FPGA-Verilog] FIFO

Description: This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
Platform: | Size: 10240 | Author: WPI | Hits:

[VHDL-FPGA-Verilog] uart_fifo

Description: 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
Platform: | Size: 150528 | Author: Xin | Hits:

[VHDL-FPGA-Verilog] t4_fifo

Description: FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test script file, we want to be useful.
Platform: | Size: 234496 | Author: 宋国志 | Hits:

[Other] fifo

Description: 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
Platform: | Size: 1024 | Author: 曹伟 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO，先进先出缓冲器，verilog源代码，包括测试代码。-FIFO, FIFO buffer, verilog source code, including test code.
Platform: | Size: 2048 | Author: 项中元 | Hits:

[Other] FIFO--verilog

Description: 同步jk触发器 实现10进制 简单易懂-jk
Platform: | Size: 1024 | Author: 王星 | Hits:

[USB develop] SLAVE-FIFO-16BITS

Description: CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
Platform: | Size: 223232 | Author: 向新铭 | Hits:

[VHDL-FPGA-Verilog] UART_RX

Description: 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
Platform: | Size: 749568 | Author: 汪静 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO
Platform: | Size: 1024 | Author: 丁海军 | Hits:

[source in ebook] fifo

Description: 基于Verilog的fifo源码，经验证，有效，实用-very good
Platform: | Size: 1024 | Author: gaojian | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Nios ii fifo,用于MCU通过nios ii进行fifo通信,verilog格式.-Nios ii fifo, for MCU FIFO communication, through the Nios II Verilog format.
Platform: | Size: 2048 | Author: 刘泽 | Hits:

[source in ebook] sync_FIFO

Description: asynchronous fifo verilog code
Platform: | Size: 1024 | Author: ian | Hits:

[VHDL-FPGA-Verilog] Synchronous-FIFO-

Description: 一个用verilog实现的同步fifo设计，压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals
Platform: | Size: 120832 | Author: csy | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 深度256的异步fifo 使用verilog语言编写的，能够实现简单的读写，存储功能！-256 the depth of asynchronous FIFO
Platform: | Size: 1024 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.
Platform: | Size: 414720 | Author: 期望 | Hits:

[Other] Syn_FIFO

Description: 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
Platform: | Size: 423936 | Author: 王蒙 | Hits:

[Other] async_fifo

Description: 异步FIFO verilog 代码 复位到空，读侧以及写侧复位均可以使两侧同时复位，且基本同时放开。-ayschronized FIFO verilog code
Platform: | Size: 5120 | Author: ruizhang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
Platform: | Size: 3777536 | Author: liyi | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
Platform: | Size: 1205248 | Author: Amy_nmw | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 关于FIFO的verilog源代码,可以很快的对FIFO做简单的了解-Verilog on the FIFO source code, you can quickly do a simple understanding of FIFO
Platform: | Size: 237568 | Author: zx | Hits:
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